register.h

SiFli chipset register definition This file provides register definition for SiFli chipset.

Author: Sifli software development team

Unnamed Group

__CM33_REV

__SAUREGION_PRESENT

__MPU_PRESENT

__VTOR_PRESENT

__NVIC_PRIO_BITS

__Vendor_SysTickConfig

__FPU_PRESENT

__DSP_PRESENT

__ICACHE_PRESENT

__DCACHE_PRESENT

MPU_REGION_NUM

CACHE_BASE

HPSYS_RCC_BASE

DMAC1_BASE

MAILBOX1_BASE

PINMUX1_BASE

USART1_BASE

USART2_BASE

EZIP_BASE

EPIC_BASE

LCDC1_BASE

I2S1_BASE

I2S2_BASE

HPSYS_CFG_BASE

EFUSEC_BASE

AES_BASE

CRC_BASE

TRNG_BASE

GPTIM1_BASE

GPTIM2_BASE

BTIM1_BASE

BTIM2_BASE

WDT1_BASE

SPI1_BASE

SPI2_BASE

EXTDMA_BASE

PSRAMC_BASE

NNACC_BASE

PDM1_BASE

PDM2_BASE

I2C1_BASE

I2C2_BASE

DSI_HOST_BASE

DSI_PHY_BASE

PTC1_BASE

BUSMON1_BASE

I2C3_BASE

HPSYS_AON_BASE

LPTIM1_BASE

GPIO1_BASE

QSPI1_BASE

QSPI2_BASE

QSPI3_BASE

SDMMC1_BASE

SDMMC2_BASE

USBC_BASE

EPIC_RAM_BASE

LPSYS_RCC_BASE

DMAC2_BASE

MAILBOX2_BASE

PINMUX2_BASE

PATCH_BASE

USART3_BASE

USART4_BASE

USART5_BASE

SPI3_BASE

SPI4_BASE

I2C4_BASE

I2C5_BASE

I2C6_BASE

LPSYS_CFG_BASE

GPTIM3_BASE

GPTIM4_BASE

GPTIM5_BASE

BTIM3_BASE

BTIM4_BASE

WDT2_BASE

GPADC_BASE

SDADC_BASE

LPCOMP_BASE

TSEN_BASE

PTC2_BASE

LCDC2_BASE

BUSMON2_BASE

LPSYS_AON_BASE

LPTIM2_BASE

LPTIM3_BASE

PMUC_BASE

RTC_BASE

IWDT_BASE

GPIO2_BASE

QSPI4_BASE

BLE_RFC_BASE

BLE_PHY_BASE

BLE_MAC_BASE

HMAILBOX_BASE

LMAILBOX_BASE

USBC_X_BASE

hwp_cache

hwp_hpsys_rcc

hwp_lpsys_rcc

hwp_dmac1

hwp_dmac2

hwp_gptim1

hwp_gptim2

hwp_gptim3

hwp_gptim4

hwp_gptim5

hwp_btim1

hwp_btim2

hwp_btim3

hwp_btim4

hwp_epic: EPIC instance

hwp_spi1

hwp_spi2

hwp_spi3

hwp_spi4

hwp_usart1

hwp_usart2

hwp_usart3

hwp_usart4

hwp_usart5

hwp_i2c1

hwp_i2c2

hwp_i2c3

hwp_i2c4

hwp_i2c5

hwp_i2c6

hwp_mailbox1

hwp_mailbox2

hwp_hmailbox

hwp_lmailbox

hwp_nnacc

hwp_dsi_host

hwp_dsi_phy

hwp_ptc1

hwp_ptc2

hwp_busmon1

hwp_busmon2

hwp_ezip: EZIP instance

hwp_efusec

hwp_rtc

hwp_pmuc

hwp_qspi1

hwp_qspi2

hwp_qspi3

hwp_qspi4

hwp_psramc

hwp_lptim1

hwp_lptim2

hwp_lptim3

hwp_hpsys_cfg

hwp_lpsys_cfg

hwp_i2s1

hwp_i2s2

hwp_pdm1

hwp_pdm2

hwp_crc

hwp_trng

hwp_lcdc1

hwp_lcdc2

hwp_extdma

hwp_sdmmc1

hwp_sdmmc2

hwp_aes_acc

hwp_gpio1: GPIO1

hwp_gpio2: GPIO2

hwp_usbc

hwp_pinmux1: PINMUX1

hwp_pinmux2: PINMUX2

hwp_hpsys_aon: HPSYS AON

hwp_lpsys_aon: LPSYS AON

hwp_gpadc1

hwp_sdadc

hwp_lpcomp

hwp_tsen

hwp_patch

hwp_ble_rfc

hwp_ble_phy

hwp_ble_mac

hwp_wdt1

hwp_wdt2

hwp_iwdt

hwp_usbc_x

USART1

USART2

USART3

USART4

USART5

DMA1

DMA2

FLASH1

FLASH2

FLASH3

FLASH4

SDIO1

SDIO2

SPI1

SPI2

SPI3

SPI4

GPTIM1

GPTIM2

GPTIM3

GPTIM4

GPTIM5

BTIM1

BTIM2

BTIM3

BTIM4

LPTIM1

LPTIM2

LPTIM3

TRNG

PSRAM

H2L_MAILBOX: HCPU2LCPU mailbox instance

HMUTEX_CH1: HCPU mutex instance channel1

HMUTEX_CH2: HCPU mutex instance channel2

L2H_MAILBOX: LCPU2HCPU mailbox instance

LMUTEX_CH1: LCPU mutex instance channel1

LMUTEX_CH2: LCPU mutex instance channel2

EPIC: EPIC instance

LCDC1

LCDC2

I2C1

I2C2

I2C3

I2C4

I2C5

I2C6

CRC

EZIP: EZIP instance

DMA1_Channel1

DMA1_Channel2

DMA1_Channel3

DMA1_Channel4

DMA1_Channel5

DMA1_Channel6

DMA1_Channel7

DMA1_Channel8

DMA1_CSELR

DMA1_CHANNEL_NUM

DMA2_Channel1

DMA2_Channel2

DMA2_Channel3

DMA2_Channel4

DMA2_Channel5

DMA2_Channel6

DMA2_Channel7

DMA2_Channel8

DMA2_CSELR

DMA2_CHANNEL_NUM

enum IRQn

Values:

enumerator NonMaskableInt_IRQn

enumerator HardFault_IRQn

enumerator MemoryManagement_IRQn

enumerator BusFault_IRQn

enumerator UsageFault_IRQn

enumerator SecureFault_IRQn

enumerator SVCall_IRQn

enumerator DebugMonitor_IRQn

enumerator PendSV_IRQn

enumerator SysTick_IRQn

enumerator AON_IRQn

enumerator BLE_MAC_IRQn

enumerator DMAC2_CH1_IRQn

enumerator DMAC2_CH2_IRQn

enumerator DMAC2_CH3_IRQn

enumerator DMAC2_CH4_IRQn

enumerator DMAC2_CH5_IRQn

enumerator DMAC2_CH6_IRQn

enumerator DMAC2_CH7_IRQn

enumerator DMAC2_CH8_IRQn

enumerator PATCH_IRQn

enumerator Interrupt11_IRQn

enumerator USART3_IRQn

enumerator USART4_IRQn

enumerator USART5_IRQn

enumerator Interrupt15_IRQn

enumerator SPI3_IRQn

enumerator SPI4_IRQn

enumerator Interrupt18_IRQn

enumerator I2C4_IRQn

enumerator I2C5_IRQn

enumerator I2C6_IRQn

enumerator GPTIM3_IRQn

enumerator GPTIM4_IRQn

enumerator GPTIM5_IRQn

enumerator BTIM3_IRQn

enumerator BTIM4_IRQn

enumerator Interrupt27_IRQn

enumerator GPADC_IRQn

enumerator SDADC_IRQn

enumerator Interrupt30_IRQn

enumerator Interrupt31_IRQn

enumerator TSEN_IRQn

enumerator PTC2_IRQn

enumerator LCDC2_IRQn

enumerator GPIO2_IRQn

enumerator QSPI4_IRQn

enumerator Interrupt37_IRQn

enumerator Interrupt38_IRQn

enumerator Interrupt39_IRQn

enumerator Interrupt40_IRQn

enumerator LPCOMP_IRQn

enumerator LPTIM2_IRQn

enumerator LPTIM3_IRQn

enumerator Interrupt44_IRQn

enumerator Interrupt45_IRQn

enumerator LPTIM1_IRQn

enumerator Interrupt47_IRQn

enumerator IWDT_IRQn

enumerator RTC_IRQn

enumerator DMAC1_CH1_IRQn

enumerator DMAC1_CH2_IRQn

enumerator DMAC1_CH3_IRQn

enumerator DMAC1_CH4_IRQn

enumerator DMAC1_CH5_IRQn

enumerator DMAC1_CH6_IRQn

enumerator DMAC1_CH7_IRQn

enumerator DMAC1_CH8_IRQn

enumerator LCPU2HCPU_IRQn

enumerator USART1_IRQn

enumerator SPI1_IRQn

enumerator I2C1_IRQn

enumerator EPIC_IRQn

enumerator LCDC1_IRQn

enumerator I2S1_IRQn

enumerator I2S2_IRQn

enumerator EFUSEC_IRQn

enumerator AES_IRQn

enumerator PTC1_IRQn

enumerator TRNG_IRQn

enumerator GPTIM1_IRQn

enumerator GPTIM2_IRQn

enumerator BTIM1_IRQn

enumerator BTIM2_IRQn

enumerator USART2_IRQn

enumerator SPI2_IRQn

enumerator I2C2_IRQn

enumerator EXTDMA_IRQn

enumerator PSRAMC_IRQn

enumerator SDMMC1_IRQn

enumerator SDMMC2_IRQn

enumerator NNACC_IRQn

enumerator PDM1_IRQn

enumerator DSIHOST_IRQn

enumerator GPIO1_IRQn

enumerator QSPI1_IRQn

enumerator QSPI2_IRQn

enumerator QSPI3_IRQn

enumerator EZIP_IRQn

enumerator PDM2_IRQn

enumerator USBC_IRQn

enumerator I2C3_IRQn

enumerator Interrupt92_IRQn

enumerator Interrupt93_IRQn

enumerator Interrupt94_IRQn

enumerator Interrupt95_IRQn

enumerator HCPU2LCPU_IRQn

typedef enum IRQn IRQn_Type

Defines

HCPU2LCPU_OFFSET: Peripheral_memory_map

LCPUROM2HCPU_OFFSET

LCPUITCM2HCPU_OFFSET

LCPUDTCM2HCPU_OFFSET

IS_FUNCTIONAL_STATE(STATE)

SET_BIT(REG, BIT)

CLEAR_BIT(REG, BIT)

READ_BIT(REG, BIT)

CLEAR_REG(REG)

WRITE_REG(REG, VAL)

READ_REG(REG)

MODIFY_REG(REG, CLEARMASK, SETMASK)

IS_LPUART_INSTANCE(INSTANCE)

HCPU_IS_SRAM_ADDR(addr)

HCPU_ADDR_2_LCPU_ADDR(addr)

Convert HCPU SRAM address which can be used by LCPU.

参数:

addr – HCPU SRAM address

返回值:

address – which can be accessed by LCPU

LCPU_ADDR_2_HCPU_ADDR(addr)

Convert LCPU SRAM address which can be used by HCPU.

参数:

addr – LCPU SRAM address

返回值:

address – which can be accessed by HCPU

LCPU_ROM_ADDR_2_HCPU_ADDR(addr)

Convert LCPU ROM address which can be used by HCPU.

参数:

addr – LCPU ROM address

返回值:

address – which can be accessed by HCPU

LCPU_ITCM_ADDR_2_HCPU_ADDR(addr)

Convert LCPU ITCM address which can be used by HCPU.

参数:

addr – LCPU ITCM address

返回值:

address – which can be accessed by HCPU

LCPU_DTCM_ADDR_2_HCPU_ADDR(addr)

Convert LCPU DTCM address which can be used by HCPU.

参数:

addr – LCPU ITCM address

返回值:

address – which can be accessed by HCPU

HCPU_MPI_SBUS_ADDR(addr)

GPADC_CALIB_FLOW_VERSION

LCPU_BOOT_ADDR

IS_LCPU(id)

Typedefs

typedef enum FlagStatus ITStatus

Enums

enum FlagStatus

Values:

enumerator RESET

enumerator SET

enum FunctionalState

Values:

enumerator DISABLE

enumerator ENABLE

enum ErrorStatus

Values:

enumerator SF_ERROR

enumerator SF_SUCCESS