bf0_hal_ptm.h

Defines

PTM_CORE_NUM: Number of cores. SF32LB57x implements 4 (CER.EN0~EN3, ISR.ERR0~ERR3), can be overridden by the build.

PTM_CORE_ANY: Passed as PTM_CoreHandleTypeDef.core to let the HAL pick a free core.

PTM_TCM_WORDS_PER_CORE: TCM slots owned by one core: core N address 0 maps to TCM[16 * N].

PTM_TCM_WORDS: Total number of TCM instruction slots: one window per core (UM5701 18.1.8).

PTM_IO_CH_NUM: Number of IO channels CH0~CH15.

PTM_EVT_NUM: Number of event flags EVT0~EVT15 (global, shared by all cores).

PTM_CORE_IRQn(core): NVIC line of a core: interrupt routing is fixed to core n <-> EVTn.

PTM_FIFO_FLAG_IFIFO_FULL: Status bits returned by HAL_PTM_CoreGetFifoStatus(). ICR.IFULL

PTM_FIFO_FLAG_IFIFO_EMPTY: ICR.IEMPTY

PTM_FIFO_FLAG_OFIFO_FULL: OCR.OFULL

PTM_FIFO_FLAG_OFIFO_EMPTY: OCR.OEMPTY

PTM_FIFO_FLAG_IFIFO_OVF: ICR.IOF, clear with HAL_PTM_CoreClearFifoFlag()

PTM_FIFO_FLAG_OFIFO_UNF: OCR.OUF, clear with HAL_PTM_CoreClearFifoFlag()

PTM_ERR_CORE: Error bits passed to PTM_ErrorCallback_t. ISR.ERRx: bus error or illegal instruction

PTM_ERR_TCM_CONFLICT: ISR.TCMx: TCM collision

Typedefs

typedef void (*PTM_CoreEventCallback_t)(struct PTM_CoreHandleTypeDef *hcore, uint16_t evt_mask)

Event callback, called from HAL_PTM_IRQHandler().

The EVT flag has already been cleared by the HAL when the callback runs.

Param hcore:: Core that raised the interrupt
Param evt_mask:: EVT bits, always the core’s own EVTn

typedef void (*PTM_ErrorCallback_t)(struct PTM_CoreHandleTypeDef *hcore, uint32_t err_mask)

Error callback, called from HAL_PTM_IRQHandler().

ISR.ERRx / ISR.TCMx cannot be cleared by writing, only CER.RSTx clears them, so the callback receives a snapshot and may call HAL_PTM_CoreReset().

Param hcore:: Core that raised the error
Param err_mask:: PTM_ERR_CORE / PTM_ERR_TCM_CONFLICT

typedef struct PTM_HandleTypeDef PTM_HandleTypeDef: Module handle, single instance owned by the HAL.

typedef struct PTM_CoreHandleTypeDef PTM_CoreHandleTypeDef

Core handle, one per user of a core.

Must have static storage duration (or live inside a device object): the HAL keeps a pointer to it for interrupt dispatch. A function local variable is not allowed.

Enums

enum PTM_StateTypeDef

PTM state, used by handles.

Values:

enumerator HAL_PTM_STATE_RESET: Not initialized

enumerator HAL_PTM_STATE_READY: Initialized, core usable

enumerator HAL_PTM_STATE_BUSY: Core claimed/running

enum PTM_RegTypeDef

General purpose register of a core, see HAL_PTM_CoreSetReg().

Values:

enumerator PTM_REG_X: 32 bit X

enumerator PTM_REG_Y: 32 bit Y

enumerator PTM_REG_A: 16 bit A (low half used)

enumerator PTM_REG_B: 16 bit B (low half used)

enumerator PTM_REG_PC: Program counter, read only

enum PTM_FifoDirTypeDef

Direction selector for the FIFO helpers.

Values:

enumerator PTM_FIFO_IFIFO: Input FIFO (IO -> memory)

enumerator PTM_FIFO_OFIFO: Output FIFO (memory -> IO)

Functions

PTM_HandleTypeDef *HAL_PTM_GetHandle(void)

Get the single PTM module handle.

返回值:: Module – handle, never NULL

HAL_StatusTypeDef HAL_PTM_Init(PTM_HandleTypeDef *hptm)

Initialize the PTM module (reference counted).

The first caller enables the clock, resets the module and clears IER/ISR. Later callers only increase the reference count, so they never disturb a core that is already running. Normally called by HAL_PTM_CoreInit().

参数:

hptm – Module handle

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_DeInit(PTM_HandleTypeDef *hptm)

Release the PTM module.

When the reference count reaches zero, every core is reset and the clock is disabled. Normally called by HAL_PTM_CoreDeInit().

参数:

hptm – Module handle

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_ForceReset(PTM_HandleTypeDef *hptm)

Reset the whole PTM module.

Stops every core, clears all their state and drops every claim and TCM record: the handles that were in use have to be released with HAL_PTM_CoreDeInit(), or re-initialized afterwards, which keeps the module reference count balanced. It must only be used when no other user of the module is active.

参数:

hptm – Module handle

返回值:

HAL_OK – if successful, otherwise error

int32_t HAL_PTM_CoreAlloc(PTM_HandleTypeDef *hptm, uint32_t core)

Claim a core.

参数:

hptm – Module handle
core – Core index 0..PTM_CORE_NUM-1, or PTM_CORE_ANY to pick a free one

返回值:

Core – index, or -1 if the requested core is busy or out of range

HAL_StatusTypeDef HAL_PTM_CoreFree(PTM_HandleTypeDef *hptm, uint32_t core)

Release a previously claimed core.

Drops its claim, its TCM record and its reporting: the interrupts of that core (IER bits and NVIC line) are switched off and it is removed from the dispatch table, so no callback is called for it afterwards.

参数:

hptm – Module handle
core – Core index

返回值:

HAL_OK – if successful, otherwise error

void HAL_PTM_IRQHandler(uint32_t core)

Handle a core interrupt.

To be called from the matching PTM1_COREn_IRQHandler(). It clears the EVT flag of that core (write 1 clear) before invoking the core callbacks, and never touches the other cores.

参数:

core – Core index

uint16_t HAL_PTM_GetEvent(PTM_HandleTypeDef *hptm)

Read the global event flags.

参数:

hptm – Module handle

返回值:

Bitmap – of EVT0~EVT15

HAL_StatusTypeDef HAL_PTM_ClearEvent(PTM_HandleTypeDef *hptm, uint16_t evt_mask)

Clear global event flags.

The CPU can only clear events, setting them is done by PTM instructions.

参数:

hptm – Module handle
evt_mask – EVT bits to clear

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_SetOutputEnable(PTM_HandleTypeDef *hptm, uint16_t ch_mask, uint16_t en_mask)

Drive the output enable of IO channels from the CPU (DOESR/DOECR).

参数:

hptm – Module handle
ch_mask – Channels to update
en_mask – Channels of ch_mask to enable, the others are disabled

返回值:

HAL_OK – if successful, otherwise error

uint16_t HAL_PTM_GetOutputEnable(PTM_HandleTypeDef *hptm)

Read back the IO channel output enable (DOER).

参数:

hptm – Module handle

返回值:

Bitmap – of the 16 channels

HAL_StatusTypeDef HAL_PTM_SetOutput(PTM_HandleTypeDef *hptm, uint16_t ch_mask, uint16_t high_mask)

Drive IO channel outputs from the CPU (DOSR/DOCR).

参数:

hptm – Module handle
ch_mask – Channels to update
high_mask – Channels of ch_mask driven high, the others low

返回值:

HAL_OK – if successful, otherwise error

uint16_t HAL_PTM_GetOutput(PTM_HandleTypeDef *hptm)

Read back the IO channel outputs (DOR).

参数:

hptm – Module handle

返回值:

Bitmap – of the 16 channels

uint32_t HAL_PTM_GetTcmConflict(PTM_HandleTypeDef *hptm)

Read the TCM collision flags (ISR.TCMx).

A core whose program exceeds 16 instructions overruns into the next core’s address 0, which raises this flag (UM5701 18.1.8). Cleared by CER.RSTx.

参数:

hptm – Module handle

返回值:

Bitmap, bit – n = core n collided

HAL_StatusTypeDef HAL_PTM_CoreInit(PTM_CoreHandleTypeDef *hcore)

Claim and reset a core, and increase the module reference count.

Must be called on a handle that is not claimed yet: an already claimed handle returns HAL_ERROR (release it with HAL_PTM_CoreDeInit() first, otherwise the core and the reference count of the previous call would leak).

参数:

hcore – Core handle with core preset (index or PTM_CORE_ANY)

返回值:

HAL_OK – if successful, HAL_BUSY if the requested core is taken, HAL_ERROR if the handle is already claimed or core is out of range

HAL_StatusTypeDef HAL_PTM_CoreDeInit(PTM_CoreHandleTypeDef *hcore)

Stop and reset a core, release it and decrease the module reference count. The handle memory must stay valid until this call returns.

参数:

hcore – Core handle

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreReset(PTM_CoreHandleTypeDef *hcore)

Reset a core: clears its registers, state and FIFO, not the TCM.

The configuration previously applied through this handle (HAL_PTM_CoreConfig() and HAL_PTM_CoreConfigIo()) is written back after the reset, so a stopped core can simply be started again. The general purpose registers, the FIFOs and the error flags are not restored, they come back cleared. The polling/interrupt mode is re-applied by HAL_PTM_CoreStart()/HAL_PTM_CoreStart_IT().

参数:

hcore – Core handle

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreStart(PTM_CoreHandleTypeDef *hcore)

Start a core in polling mode.

The completion event is enabled (IER.EVTAUTOx) so that HAL_PTM_CoreWaitDone() and HAL_PTM_CoreWaitEvent() can observe the end of the task, any interrupt of that core is switched off, and the event flag of the core is cleared so that a completion left over by a previous run cannot be mistaken for this one. This is the counterpart of HAL_PTM_CoreStart_IT().

参数:

hcore – Core handle

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreStart_IT(PTM_CoreHandleTypeDef *hcore)

Start a core in interrupt mode.

Enables the completion and error interrupts of the core (IER.EVTAUTOx | IER.EVTIE<x> | IER.ERRIE<x>) together with its NVIC line, so the callbacks registered with HAL_PTM_CoreRegisterCallback() are called when the task completes, when the program raises an event, or when the core reports an error. The event flag of the core is cleared first, which also avoids an interrupt from a completion left over by a previous run. This is the counterpart of HAL_PTM_CoreStart().

参数:

hcore – Core handle

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreStop(PTM_CoreHandleTypeDef *hcore)

Stop a core.

参数:

hcore – Core handle

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreStartMask(PTM_HandleTypeDef *hptm, uint32_t core_mask, uint32_t it_mask)

Enable several cores with a single CER write, each one in its own mode.

All the cores of core_mask are enabled by the same register write, i.e. in the same hclk cycle, which is the closest thing to a simultaneous start. The mode is chosen per core: the ones also set in it_mask behave like HAL_PTM_CoreStart_IT() (completion, event and error interrupts), the others like HAL_PTM_CoreStart() (completion event only, no interrupt). A helper core that nobody waits for can therefore be started together with the master without generating interrupts.

HAL_PTM_CoreStartMask(hptm, (1U << 0) | (1U << 1), (1U << 0));
// core0 and core1 start in the same cycle, only core0 interrupts the CPU

参数:

hptm – Module handle
core_mask – Bit n enables core n
it_mask – Bit n: core n reports through interrupts. Bits outside core_mask are ignored

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreStopMask(PTM_HandleTypeDef *hptm, uint32_t core_mask)

Stop several cores with a single CER write.

参数:

hptm – Module handle
core_mask – Bit n stops core n

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreStep(PTM_CoreHandleTypeDef *hcore)

Single step a stopped core.

If the stepped instruction stalls the pipeline (WAIT, blocked FIFO…), the step does not complete until the condition disappears (UM5701 18.1.25).

参数:

hcore – Core handle

返回值:

HAL_OK – if successful, otherwise error

uint32_t HAL_PTM_CoreIsRunning(PTM_CoreHandleTypeDef *hcore)

Check whether a core is running (CER.ENx read back).

参数:

hcore – Core handle

返回值:

1 – if running, 0 if stopped

HAL_StatusTypeDef HAL_PTM_CoreConfig(PTM_CoreHandleTypeDef *hcore, const PTM_CoreCfgTypeDef *cfg)

Configure CCRx: clock divider, repetition and end addresses.

参数:

hcore – Core handle
cfg – Configuration to apply

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreConfigIo(PTM_CoreHandleTypeDef *hcore, const PTM_IoFifoInitTypeDef *cfg)

Configure ICRx/OCR: FIFO, IO mapping and shift settings.

参数:

hcore – Core handle
cfg – Configuration to apply

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreLoadCode(PTM_CoreHandleTypeDef *hcore, const uint32_t *code, uint32_t words)

Load a program into the TCM window of a core.

The TCM mapping of UM5701 18.1.8 is applied: core N address 0 is TCM[16*N]. A program longer than PTM_TCM_WORDS_PER_CORE instructions overruns into the address 0 of the following cores; the HAL records which core owns which TCM slot and refuses (HAL_ERROR, nothing written) any load that would overwrite the program of another core. That covers both orders: loading over the window of an already claimed core, and claiming a core whose window was already overrun by a longer program loaded earlier.

参数:

hcore – Core handle
code – Instruction words, usually built with ptm_ins.h or ptm_asm.h
words – Number of words, 1..PTM_TCM_WORDS

返回值:

HAL_OK – if successful, HAL_ERROR if another core owns part of the range, HAL_BUSY if the core is running (load the program before starting the core)

uint32_t *HAL_PTM_CoreGetTcmPtr(PTM_CoreHandleTypeDef *hcore)

Get the TCM window of a core, i.e. the address its PC=0 maps to.

Advanced use only: writing through this pointer bypasses the ownership tracking of HAL_PTM_CoreLoadCode(), so the overrun protection of the TCM is lost for that program. It also does not wrap: a program longer than PTM_TCM_WORDS_PER_CORE instructions has to be loaded with HAL_PTM_CoreLoadCode(), which applies the TCM mapping of UM5701 18.1.8.

参数:

hcore – Core handle

返回值:

Pointer – into TCM, word aligned

HAL_StatusTypeDef HAL_PTM_CoreSetReg(PTM_CoreHandleTypeDef *hcore, PTM_RegTypeDef reg, uint32_t value)

Read or write a general purpose register of a core.

参数:

hcore – Core handle
reg – Register selector
value – Value to write (set only)

返回值:

HAL_OK – if successful, otherwise error

uint32_t HAL_PTM_CoreGetReg(PTM_CoreHandleTypeDef *hcore, PTM_RegTypeDef reg)

Read a general purpose register of a core.

参数:

hcore – Core handle
reg – Register selector, PTM_REG_PC reads PCx

返回值:

Register – value, 0 if the handle is invalid

HAL_StatusTypeDef HAL_PTM_CorePushOFifo(PTM_CoreHandleTypeDef *hcore, uint32_t data)

Push one word into the output FIFO (OFIFOx).

Like a UART transmit FIFO, this function does not look at the FIFO status: the caller checks that there is room first with HAL_PTM_CoreGetFifoStatus() (PTM_FIFO_FLAG_OFIFO_FULL clear in the returned bitmap). Writing to a full FIFO has no behaviour defined by the manual and must be avoided.

A FIFO belongs to the task engine of a core, so it only takes data once that core is enabled by HAL_PTM_CoreStart() / HAL_PTM_CoreStart_IT(): a core that was only initialized is still held by the CER.RSTx written in HAL_PTM_CoreReset() and silently drops the writes.

参数:

hcore – Core handle
data – Word to push

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CorePopIFifo(PTM_CoreHandleTypeDef *hcore, uint32_t *data)

Pop one word from the input FIFO (IFIFOx).

Same convention as HAL_PTM_CorePushOFifo(): the FIFO status is not checked here, the caller confirms that data is available first with HAL_PTM_CoreGetFifoStatus() (PTM_FIFO_FLAG_IFIFO_EMPTY clear). Reading an empty FIFO has no behaviour defined by the manual and must be avoided.

参数:

hcore – Core handle
data – Destination of the popped word

返回值:

HAL_OK – if successful, otherwise error

uint32_t HAL_PTM_CoreGetFifoStatus(PTM_CoreHandleTypeDef *hcore)

Read the FIFO status of a core.

参数:

hcore – Core handle

返回值:

Bitmap – of PTM_FIFO_FLAG_xxx

HAL_StatusTypeDef HAL_PTM_CoreClearFifoFlag(PTM_CoreHandleTypeDef *hcore, uint32_t flag_mask)

Clear the FIFO overflow/underflow flags.

Requires HAL_PTM_CoreConfigIo() to have been called: the configuration is rewritten from the shadow copy, because ICR/OCR configuration bits are not preserved by a write 1 clear of IOF/OUF.

参数:

hcore – Core handle
flag_mask – PTM_FIFO_FLAG_IFIFO_OVF / PTM_FIFO_FLAG_OFIFO_UNF

返回值:

HAL_OK – if successful, otherwise error

uint32_t HAL_PTM_CoreGetFifoAddr(PTM_CoreHandleTypeDef *hcore, PTM_FifoDirTypeDef dir)

Get the FIFO register address, to be used as the peripheral address of a DMA transfer (the DMA request numbers are PTM1_IFIFOn_DMA_REQUEST and PTM1_OFIFOn_DMA_REQUEST, see the board dma_config.h).

参数:

hcore – Core handle
dir – FIFO direction

返回值:

Register – address, 0 if the handle is invalid

HAL_StatusTypeDef HAL_PTM_CoreGetStatus(PTM_CoreHandleTypeDef *hcore, PTM_CoreStatusTypeDef *status)

Read the status of a core.

参数:

hcore – Core handle
status – Destination structure

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreRegisterCallback(PTM_CoreHandleTypeDef *hcore, PTM_CoreEventCallback_t evt_cb, PTM_ErrorCallback_t err_cb)

Only the handle itself is checked, so the callbacks may be registered before HAL_PTM_CoreInit(): HAL_PTM_CoreInit() keeps them.

The event callback runs after the HAL has cleared the event flag of the core. The error callback runs after the HAL has masked the error interrupt of that core (the ERRx/TCMx flags are level and can only be cleared by CER.RSTx), so an error callback that wants to continue has to call HAL_PTM_CoreReset() and start the core again, which re-arms the interrupt.

参数:

hcore – Core handle
evt_cb – Event callback, may be NULL
err_cb – Error callback, may be NULL

返回值:

HAL_OK – if successful, otherwise error

HAL_StatusTypeDef HAL_PTM_CoreWaitEvent(PTM_CoreHandleTypeDef *hcore, uint32_t timeout_ms)

Polling wait for the event of a core, without using interrupts.

Reads the global EVT flags until the own EVTn of the core is set, consumes it (same semantics as HAL_PTM_IRQHandler()) and returns. Blocking call, to be used from thread context; in interrupt mode use the callbacks instead.

参数:

hcore – Core handle
timeout_ms – Timeout in ms, HAL_MAX_DELAY to wait indefinitely

返回值:

HAL_OK – when the event was consumed, HAL_TIMEOUT on timeout

HAL_StatusTypeDef HAL_PTM_CoreWaitDone(PTM_CoreHandleTypeDef *hcore, uint32_t timeout_ms)

Polling wait for the end of the task, without using interrupts.

Waits on the flags the hardware uses to report the run, exactly like the interrupt mode does: EVTn is set when the task completes (IER.EVTAUTOx is enabled by HAL_PTM_CoreStart()/HAL_PTM_CoreStart_IT()) and ISR.ERRx/TCMx are set when the run is aborted. The event is left pending, so HAL_PTM_CoreWaitEvent() or HAL_PTM_GetEvent() still observe it afterwards. Blocking call, thread context only.

switch (HAL_PTM_CoreWaitDone(&hcore, 1000))
{
case HAL_OK:      break;      // the task completed
case HAL_ERROR:   break;      // aborted: bus/instruction error or TCM collision
case HAL_TIMEOUT: break;      // not finished: still running, or stopped on purpose
default:          break;
}

参数:

hcore – Core handle
timeout_ms – Timeout in ms, HAL_MAX_DELAY to wait indefinitely

返回值:

HAL_OK – the task completed. HAL_ERROR: the run was aborted, the details are in HAL_PTM_CoreGetStatus(). HAL_TIMEOUT: neither a completion nor an error before the timeout, for example a program that never ends or a core stopped with HAL_PTM_CoreStop().

void HAL_PTM_CoreEventCallback(PTM_CoreHandleTypeDef *hcore, uint16_t evt_mask)

Default event callback, does nothing.

参数:

hcore – Core handle
evt_mask – Event bits

void HAL_PTM_ErrorCallback(PTM_CoreHandleTypeDef *hcore, uint32_t err_mask)

Default error callback, does nothing.

参数:

hcore – Core handle
err_mask – Error bits

struct PTM_CoreCfgTypeDef

#include <bf0_hal_ptm.h>

Core configuration, written to CCRx (UM5701 18.1.5, 18.1.26).

Public Members

uint8_t psc: Core clock = hclk / (psc + 1), 0..255

uint8_t rep: 0: run once, 1..254: repeat, 255: forever

uint8_t end0: TCM instruction index ending the sequence: the instruction at that index runs, and the sequence ends right after it. 0 means “no end check at this index”

uint8_t end1: Second end index, for the other branch

struct PTM_IoFifoInitTypeDef

#include <bf0_hal_ptm.h>

Per core IO/FIFO configuration, written to ICRx and OCRx (UM5701 18.1.19 ~ 18.1.22).

Public Members

uint8_t ififo_en: Enable IFIFO, depth 4 or 8

uint8_t iauto: Y -> IFIFO automatic push

uint8_t ibase: IN[n] = CH[(n + ibase) % 16]

uint8_t irsh: Input shift direction, 0: shift left

uint8_t iblock: Stall the pipeline when IFIFO is full

uint8_t ishift: Extra shift before pushing to IFIFO

uint8_t ilimit: Accumulated input bit count that triggers the automatic push (ICRx.ILIMIT). Note that 0 means 32, not “every sample”: Y_CNT >= ilimit pushes Y.

uint8_t ofifo_en: Enable OFIFO, depth 4 or 8

uint8_t oauto: OFIFO -> X automatic pop

uint8_t obase: CH[(n + obase) % 16] = OUT[n]

uint8_t orsh: Output shift direction, 0: shift left

uint8_t oblock: Stall the pipeline when OFIFO is empty

uint8_t oshift: Extra shift after popping from OFIFO

uint8_t olimit: Output bit count that triggers the auto pop (OCRx.OLIMIT); 0 means 32, the same convention as ilimit.

struct PTM_CoreStatusTypeDef

#include <bf0_hal_ptm.h>

Snapshot of one core, see HAL_PTM_CoreGetStatus().

Public Members

uint32_t pc: PCx

uint8_t running: CER.ENx read back

uint8_t error: ISR.ERRx: bus error or illegal instruction

uint8_t tcm_conflict: ISR.TCMx

uint8_t reserved

struct PTM_HandleTypeDef

#include <bf0_hal_ptm.h>

Module handle, single instance owned by the HAL.

Public Members

PTM_TypeDef *Instance: PTM register base (= hwp_ptm1)

PTM_StateTypeDef State: Module state

uint8_t core_bitmap: Claimed cores, bit n = core n

uint8_t init_cnt: Reference count of HAL_PTM_Init()

struct PTM_CoreHandleTypeDef

#include <bf0_hal_ptm.h>

Core handle, one per user of a core.

Must have static storage duration (or live inside a device object): the HAL keeps a pointer to it for interrupt dispatch. A function local variable is not allowed.

Public Members

PTM_HandleTypeDef *hptm: Filled by HAL_PTM_CoreInit()

uint32_t core: Core index, or PTM_CORE_ANY

PTM_CoreCfgTypeDef Init: Last CCRx configuration

PTM_IoFifoInitTypeDef IoInit: Last ICRx/OCR configuration

PTM_CoreEventCallback_t EventCallback: May be NULL

PTM_ErrorCallback_t ErrorCallback: May be NULL

PTM_StateTypeDef State: Core state

uint8_t io_configured: IoInit has been written